1. Field
The present invention relates to a method of manufacturing a semiconductor device that includes a drift layer having a super-junction structure formed of an alternating conductivity type layer including n-type regions and p-type regions arranged alternately (hereinafter referred to as a “super-junction semiconductor device” and abbreviated to “SJ semiconductor device”). Specifically, the invention relates to a method of manufacturing an SJ MOS semiconductor device having a trench-gate structure.
2. Description of the Related Art
The SJ MOS semiconductor device, the cross sectional view thereof is shown in FIG. 5(a), is a SJ-MOSFET provided with a trench-gate structure. The trench-gate SJ-MOSFET shown in FIG. 5(a) includes n+ silicon semiconductor substrate 101 and a drift layer on n+ silicon semiconductor substrate 101. The drift layer includes alternating-conductivity-type layer 104 including p-type region 102 and n-type region 103, both extending in perpendicular to the substrate 101 major surface. Regions corresponding to p-type region 102 and n-type region 103 are arranged alternately and repeatedly in parallel to the substrate 101 major surface such that p-type region 102 and n-type region 103 are adjoining to each other.
The trench-gate SJ-MOSFET further includes trench gate 105, the bottom thereof is positioned in the upper portion of n-type region 103, and p-type channel region 106 on alternating-conductivity-type layer 104. The p-type channel region 106 is sandwiched between trench gates 105. The trench-gate SJ-MOSFET also includes n+ source region 107 and p+ contact region 108, both on p-type channel region 106. The n+ source region 107 is in contact with the trench gate 5 side wall. The p+ contact region 108 is sandwiched between n+ source regions 107. Trench-gate SJ-MOSFET 100 has the structure as described above.
In manufacturing trench-gate SJ-MOSFET 100, a p-type epitaxial layer is usually formed on the entire upper surface of heavily doped n+ silicon semiconductor substrate 101. A plurality of third trenches (the trenches for forming alternating conductivity type layer 104) deep enough to reach n+ silicon semiconductor substrate 101 is formed through the p-type epitaxial layer. An n-type epitaxial layer is buried in the third trenches to form buried n-type regions 103. The portions of the p-type epitaxial layer remaining between the third trenches provide p-type regions 102. The layer structure, in which a couple of p-type region 102 and n-type region 103 adjoining to each other is repeated, provides alternating conductivity type layer 104 having a super-junction structure specific to the drift layer in the SJ semiconductor device.
From the surface of each n-type region 103 in alternating conductivity type layer 104, a second trench (a trench for forming a trench gate) narrower than n-type region 103 is formed. Then, a trench gate structure is formed by burying a gate electrode made from polycrystalline silicon and such a material exhibiting low electrical resistance in the second trench with a gate insulator film interposed between the second trench and the gate electrode.
Then, p-type channel region 106 is formed in the surface portion of alternating conductivity type layer 104 such that p-type channel region 106 is positioned more shallowly than the second trench. Further, p+ contact region 108 is formed in the surface portion of p-type channel region 106. Further more, n+ source region 107 is formed in the surface portion of p+ contact region 108 such that n+ source region 107 is in contact with the second trench side wall. Thus, the second trench for forming trench gate 105 is set to be narrower than the third trench for forming n-type region 103.
If trench gate 105 is arranged properly in the upper portion of n-type region 103, the portions of n-type region 103 on both sides of trench gate 105 will be almost the same in width. If the layer arrangement described above is formed by the multi-step epitaxial growth method, the arrangement deviation as described in FIG. 5(c) will be liable and the proper arrangement as described in FIG. 5(b) will be obtained hardly. If the arrangement deviates from the proper one, the ON-state resistance will increase.
For obviating the problems caused by the arrangement deviation as described above, Japanese Unexamined Patent Application Publication Nos. 2009-200300 and 2003-124464 propose a method of manufacturing a semiconductor device that prevents the arrangement deviation from causing by using a same oxide film mask for the mask to form the third trench for forming n-type region 103 in alternating conductivity type layer 104 and for the mask to form the second trench for forming the trench gate.
If the widths of the third and second trenches are the same, p-type region 102 in alternating conductivity type layer 104 will be in contact with the trench gate inevitably. Therefore, a channel is caused in the portion of p-type region 102 in contact with the trench gate, elongating the channel length and increasing the ON-state resistance.
For avoiding the ON-state resistance increase, it is necessary to form n-type buffer region 109 by ion implantation and by thermal diffusion, as shown in FIG. 6, in the portion in which p-type region 102 and the trench gate 105 side wall are in contact with each other. However, buffer region 109 expands easily by diffusion and overlaps the adjacent buffer region 109 easily. If adjacent buffer regions 109 overlap each other, p-type region 102 in alternating conductivity type layer 104 is separated from p-type channel region 106, resulting in a floating potential state. If p-type region 102 is brought into a floating potential state, the breakdown voltage will be unstable. If adjacent buffer regions 109 are spaced apart from each other so as not to overlap each other, it will be hazardous for reducing the repeating pitch in alternating conductivity type layer 104.
For avoiding the problems caused by setting the second trench and the third trench to be the same in width, it is necessary to set the mask for forming the third trench to be wider than the mask for forming the second trench. However, if the mask for forming the third trench is set to be wider than the mask for forming the second trench simply, the problem of mask alignment deviation will not be obviated as described above.
If the mask used to form the second trench for forming the trench gate deviates from the proper position, the portions of n-type region 103 on both sides of the trench gate trench will not be the same in width as shown in FIG. 5(c). The portion of n-type region 103 on one side of the trench gate trench will be extremely narrow or no longer remaining. As a result, the channel resistance or the JFET resistance will increase and the ON-state resistance may increase.
If one wants to prevent a mask alignment deviation in the conventional structure, it is necessary to consider a certain mask alignment deviation in determining the n-type region 103 width and to set the n-type region 103 width to be wider by the mask alignment deviation considered. However, the n-type region 103 width set to be wider is hazardous for reducing the repeating pitch in alternating conductivity type layer 104 due to the restriction by the size rule of the second trench on the surface structure.
In view of the foregoing, it is a first object of the invention to obviate the problems described above. It is a second object of the invention to provide a method of manufacturing a super-junction semiconductor device that facilitates preventing the mutual positional deviation from causing between the region of a first conductivity type in an alternating conductivity type layer and the second trench for forming a trench gate. It is a third object of the invention to provide a method of manufacturing a super-junction semiconductor device that facilitates preventing the ON-state resistance from increasing greatly without causing any hazard for reducing the repeating pitch in the alternating conductivity type layer, even if the second trench for forming a trench gate is displaced for more than the width of the region of the first conductivity type in an alternating conductivity type layer.